GBDK 2020 Docs  4.1.1
API Documentation for GBDK 2020
hardware.h
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1 
7 #ifndef _HARDWARE_H
8 #define _HARDWARE_H
9 
10 #include <types.h>
11 
12 #define __BYTES extern UBYTE
13 #define __BYTE_REG extern volatile UBYTE
14 #define __REG extern volatile SFR
15 
31 
38 
42 #define rP1 P1_REG
43 
44 #define P1F_5 0b00100000
45 #define P1F_4 0b00010000
46 #define P1F_3 0b00001000
47 #define P1F_2 0b00000100
48 #define P1F_1 0b00000010
49 #define P1F_0 0b00000001
50 
51 #define P1F_GET_DPAD P1F_5
52 #define P1F_GET_BTN P1F_4
53 #define P1F_GET_NONE (P1F_4 | P1F_5)
54 
56 #define rSB SB_REG
58 #define rSC SC_REG
60 #define rDIV DIV_REG
62 #define rTIMA TIMA_REG
64 #define rTMA TMA_REG
66 #define rTAC TAC_REG
67 
68 #define TACF_START 0b00000100
69 #define TACF_STOP 0b00000000
70 #define TACF_4KHZ 0b00000000
71 #define TACF_16KHZ 0b00000011
72 #define TACF_65KHZ 0b00000010
73 #define TACF_262KHZ 0b00000001
74 
75 #define SIOF_CLOCK_EXT 0b00000000
76 #define SIOF_CLOCK_INT 0b00000001
77 #define SIOF_SPEED_1X 0b00000000
78 #define SIOF_SPEED_32X 0b00000010
79 #define SIOF_XFER_START 0b10000000
80 #define SIOF_B_CLOCK 0
81 #define SIOF_B_SPEED 1
82 #define SIOF_B_XFER_START 7
83 
85 #define rIF IF_REG
86 
88 #define rAUD1SWEEP NR10_REG
89 #define AUD1SWEEP_UP 0b00000000
90 #define AUD1SWEEP_DOWN 0b00001000
91 #define AUD1SWEEP_TIME(x) ((x) << 4)
92 #define AUD1SWEEP_LENGTH(x) (x)
94 #define rAUD1LEN NR11_REG
96 #define rAUD1ENV NR12_REG
98 #define rAUD1LOW NR13_REG
100 #define rAUD1HIGH NR14_REG
101 
103 #define rAUD2LEN NR21_REG
105 #define rAUD2ENV NR22_REG
107 #define rAUD2LOW NR23_REG
109 #define rAUD2HIGH NR24_REG
110 
112 #define rAUD3ENA NR30_REG
114 #define rAUD3LEN NR31_REG
116 #define rAUD3LEVEL NR32_REG
118 #define rAUD3LOW NR33_REG
120 #define rAUD3HIGH NR34_REG
121 
123 #define rAUD4LEN NR41_REG
125 #define rAUD4ENV NR42_REG
127 #define rAUD4POLY NR43_REG
128 #define AUD4POLY_WIDTH_15BIT 0x00
129 #define AUD4POLY_WIDTH_7BIT 0x08
131 #define rAUD4GO NR44_REG
132 
134 #define rAUDVOL NR50_REG
135 
136 #define AUDVOL_VOL_LEFT(x) ((x) << 4)
137 #define AUDVOL_VOL_RIGHT(x) ((x))
138 #define AUDVOL_VIN_LEFT 0b10000000
139 #define AUDVOL_VIN_RIGHT 0b00001000
140 
142 #define rAUDTERM NR51_REG
143 
144 #define AUDTERM_4_LEFT 0b10000000
145 #define AUDTERM_3_LEFT 0b01000000
146 #define AUDTERM_2_LEFT 0b00100000
147 #define AUDTERM_1_LEFT 0b00010000
148 #define AUDTERM_4_RIGHT 0b00001000
149 #define AUDTERM_3_RIGHT 0b00000100
150 #define AUDTERM_2_RIGHT 0b00000010
151 #define AUDTERM_1_RIGHT 0b00000001
152 
154 #define rAUDENA NR52_REG
155 
156 #define AUDENA_ON 0b10000000
157 #define AUDENA_OFF 0b00000000
158 
161 
163 #define rLCDC LCDC_REG
164 
165 #if defined(__TARGET_ap)
166 #define LCDCF_OFF 0b00000000
167 #define LCDCF_ON 0b00000001
168 #define LCDCF_WIN9800 0b00000000
169 #define LCDCF_WIN9C00 0b00000010
170 #define LCDCF_WINOFF 0b00000000
171 #define LCDCF_WINON 0b00000100
172 #define LCDCF_BG8800 0b00000000
173 #define LCDCF_BG8000 0b00001000
174 #define LCDCF_BG9800 0b00000000
175 #define LCDCF_BG9C00 0b00010000
176 #define LCDCF_OBJ8 0b00000000
177 #define LCDCF_OBJ16 0b00100000
178 #define LCDCF_OBJOFF 0b00000000
179 #define LCDCF_OBJON 0b01000000
180 #define LCDCF_BGOFF 0b00000000
181 #define LCDCF_BGON 0b10000000
182 #define LCDCF_B_ON 0
183 #define LCDCF_B_WIN9C00 1
184 #define LCDCF_B_WINON 2
185 #define LCDCF_B_BG8000 3
186 #define LCDCF_B_BG9C00 4
187 #define LCDCF_B_OBJ16 5
188 #define LCDCF_B_OBJON 6
189 #define LCDCF_B_BGON 7
190 #elif defined(__TARGET_duck)
191 #define LCDCF_OFF 0b00000000
192 #define LCDCF_ON 0b10000000
193 #define LCDCF_WIN9800 0b00000000
194 #define LCDCF_WIN9C00 0b00001000
195 #define LCDCF_WINOFF 0b00000000
196 #define LCDCF_WINON 0b00100000
197 #define LCDCF_BG8800 0b00000000
198 #define LCDCF_BG8000 0b00010000
199 #define LCDCF_BG9800 0b00000000
200 #define LCDCF_BG9C00 0b00000100
201 #define LCDCF_OBJ8 0b00000000
202 #define LCDCF_OBJ16 0b00000010
203 #define LCDCF_OBJOFF 0b00000000
204 #define LCDCF_OBJON 0b00000001
205 #define LCDCF_BGOFF 0b00000000
206 #define LCDCF_BGON 0b01000000
207 #define LCDCF_B_ON 7
208 #define LCDCF_B_WIN9C00 3
209 #define LCDCF_B_WINON 5
210 #define LCDCF_B_BG8000 4
211 #define LCDCF_B_BG9C00 2
212 #define LCDCF_B_OBJ16 1
213 #define LCDCF_B_OBJON 0
214 #define LCDCF_B_BGON 6
215 #else
216 #define LCDCF_OFF 0b00000000
217 #define LCDCF_ON 0b10000000
218 #define LCDCF_WIN9800 0b00000000
219 #define LCDCF_WIN9C00 0b01000000
220 #define LCDCF_WINOFF 0b00000000
221 #define LCDCF_WINON 0b00100000
222 #define LCDCF_BG8800 0b00000000
223 #define LCDCF_BG8000 0b00010000
224 #define LCDCF_BG9800 0b00000000
225 #define LCDCF_BG9C00 0b00001000
226 #define LCDCF_OBJ8 0b00000000
227 #define LCDCF_OBJ16 0b00000100
228 #define LCDCF_OBJOFF 0b00000000
229 #define LCDCF_OBJON 0b00000010
230 #define LCDCF_BGOFF 0b00000000
231 #define LCDCF_BGON 0b00000001
232 #define LCDCF_B_ON 7
233 #define LCDCF_B_WIN9C00 6
234 #define LCDCF_B_WINON 5
235 #define LCDCF_B_BG8000 4
236 #define LCDCF_B_BG9C00 3
237 #define LCDCF_B_OBJ16 2
238 #define LCDCF_B_OBJON 1
239 #define LCDCF_B_BGON 0
240 #endif
241 
243 #define rSTAT STAT_REG
244 
245 #if defined(__TARGET_ap)
246 #define STATF_LYC 0b00000010
247 #define STATF_MODE10 0b00000100
248 #define STATF_MODE01 0b00001000
249 #define STATF_MODE00 0b00010000
250 #define STATF_LYCF 0b00100000
251 #define STATF_HBL 0b00000000
252 #define STATF_VBL 0b10000000
253 #define STATF_OAM 0b01000000
254 #define STATF_LCD 0b11000000
255 #define STATF_BUSY 0b01000000
256 #define STATF_B_LYC 1
257 #define STATF_B_MODE10 2
258 #define STATF_B_MODE01 3
259 #define STATF_B_MODE00 4
260 #define STATF_B_LYCF 5
261 #define STATF_B_VBL 7
262 #define STATF_B_OAM 6
263 #define STATF_B_BUSY 6
264 #else
265 #define STATF_LYC 0b01000000
266 #define STATF_MODE10 0b00100000
267 #define STATF_MODE01 0b00010000
268 #define STATF_MODE00 0b00001000
269 #define STATF_LYCF 0b00000100
270 #define STATF_HBL 0b00000000
271 #define STATF_VBL 0b00000001
272 #define STATF_OAM 0b00000010
273 #define STATF_LCD 0b00000011
274 #define STATF_BUSY 0b00000010
275 #define STATF_B_LYC 6
276 #define STATF_B_MODE10 5
277 #define STATF_B_MODE01 4
278 #define STATF_B_MODE00 3
279 #define STATF_B_LYCF 2
280 #define STATF_B_VBL 0
281 #define STATF_B_OAM 1
282 #define STATF_B_BUSY 1
283 #endif
284 
286 #define rSCY
288 #define rSCX SCX_REG
290 #define rLY LY_REG
292 #define rLYC LYC_REG
294 #define rDMA DMA_REG
296 #define rBGP BGP_REG
298 #define rOBP0 OBP0_REG
300 #define rOBP1 OBP1_REG
302 #define rWY WY_REG
304 #define rWX WX_REG
306 #define rKEY1 KEY1_REG
307 #define rSPD KEY1_REG
308 
309 #define KEY1F_DBLSPEED 0b10000000
310 #define KEY1F_PREPARE 0b00000001
311 
313 #define rVBK VBK_REG
314 
315 #define VBK_BANK_0 0
316 #define VBK_TILES 0
317 #define VBK_BANK_1 1
318 #define VBK_ATTRIBUTES 1
320 #define BKGF_PRI 0b10000000
321 #define BKGF_YFLIP 0b01000000
322 #define BKGF_XFLIP 0b00100000
323 #define BKGF_BANK0 0b00000000
324 #define BKGF_BANK1 0b00001000
326 #define BKGF_CGB_PAL0 0b00000000
327 #define BKGF_CGB_PAL1 0b00000001
328 #define BKGF_CGB_PAL2 0b00000010
329 #define BKGF_CGB_PAL3 0b00000011
330 #define BKGF_CGB_PAL4 0b00000100
331 #define BKGF_CGB_PAL5 0b00000101
332 #define BKGF_CGB_PAL6 0b00000110
333 #define BKGF_CGB_PAL7 0b00000111
336 #define rHDMA1 HDMA1_REG
338 #define rHDMA2 HDMA2_REG
340 #define rHDMA3 HDMA3_REG
342 #define rHDMA4 HDMA4_REG
344 #define rHDMA5 HDMA5_REG
345 
346 #define HDMA5F_MODE_GP 0b00000000
347 #define HDMA5F_MODE_HBL 0b10000000
348 
349 #define HDMA5F_BUSY 0b10000000
350 
352 #define rRP RP_REG
353 
354 #define RPF_ENREAD 0b11000000
355 #define RPF_DATAIN 0b00000010
356 #define RPF_WRITE_HI 0b00000001
357 #define RPF_WRITE_LO 0b00000000
358 
360 #define rBCPS BCPS_REG
361 
362 #define BCPSF_AUTOINC 0b10000000
364 #define rBCPD BCPD_REG
365 
367 #define rOCPS OCPS_REG
368 
369 #define OCPSF_AUTOINC 0b10000000
371 #define rOCPD OCPD_REG
373 #define rSVBK SVBK_REG
374 #define rSMBK SVBK_REG
375 
377 #define rPCM12 PCM12_REG
378 
380 #define rPCM34 PCM34_REG
381 
383 #define rIE IE_REG
384 
385 #define IEF_HILO 0b00010000
386 #define IEF_SERIAL 0b00001000
387 #define IEF_TIMER 0b00000100
388 #define IEF_STAT 0b00000010
389 #define IEF_VBLANK 0b00000001
390 
391 
392 /* Square wave duty cycle */
393 #define AUDLEN_DUTY_12_5 0b00000000
394 #define AUDLEN_DUTY_25 0b01000000
395 #define AUDLEN_DUTY_50 0b10000000
396 #define AUDLEN_DUTY_75 0b11000000
397 #define AUDLEN_LENGTH(x) (x)
398 
399 /* Audio envelope flags */
400 #define AUDENV_VOL(x) ((x) << 4)
401 #define AUDENV_UP 0b00001000
402 #define AUDENV_DOWN 0b00000000
403 #define AUDENV_LENGTH(x) (x)
404 
405 /* Audio trigger flags */
406 #define AUDHIGH_RESTART 0b10000000
407 #define AUDHIGH_LENGTH_ON 0b01000000
408 #define AUDHIGH_LENGTH_OFF 0b00000000
409 
410 /* OAM attributes flags */
411 #define OAMF_PRI 0b10000000
412 #define OAMF_YFLIP 0b01000000
413 #define OAMF_XFLIP 0b00100000
414 #define OAMF_PAL0 0b00000000
415 #define OAMF_PAL1 0b00010000
416 #define OAMF_BANK0 0b00000000
417 #define OAMF_BANK1 0b00001000
419 #define OAMF_CGB_PAL0 0b00000000
420 #define OAMF_CGB_PAL1 0b00000001
421 #define OAMF_CGB_PAL2 0b00000010
422 #define OAMF_CGB_PAL3 0b00000011
423 #define OAMF_CGB_PAL4 0b00000100
424 #define OAMF_CGB_PAL5 0b00000101
425 #define OAMF_CGB_PAL6 0b00000110
426 #define OAMF_CGB_PAL7 0b00000111
428 #define OAMF_PALMASK 0b00000111
430 #define DEVICE_SCREEN_X_OFFSET 0
431 #define DEVICE_SCREEN_Y_OFFSET 0
432 #define DEVICE_SCREEN_WIDTH 20
433 #define DEVICE_SCREEN_HEIGHT 18
434 #define DEVICE_SCREEN_BUFFER_WIDTH 32
435 #define DEVICE_SCREEN_BUFFER_HEIGHT 32
436 #define DEVICE_SCREEN_MAP_ENTRY_SIZE 1
437 #define DEVICE_SPRITE_PX_OFFSET_X 8
438 #define DEVICE_SPRITE_PX_OFFSET_Y 16
439 #define DEVICE_WINDOW_PX_OFFSET_X 7
440 #define DEVICE_WINDOW_PX_OFFSET_Y 0
441 #define DEVICE_SCREEN_PX_WIDTH (DEVICE_SCREEN_WIDTH * 8)
442 #define DEVICE_SCREEN_PX_HEIGHT (DEVICE_SCREEN_HEIGHT * 8)
444 #endif
__BYTE_REG rROMB1
Definition: hardware.h:36
__REG NR33_REG
Definition: hardware.h:117
__REG NR14_REG
Definition: hardware.h:99
__REG P1_REG
Definition: hardware.h:41
__BYTES _SRAM[]
Definition: hardware.h:24
#define __REG
Definition: hardware.h:14
__REG SC_REG
Definition: hardware.h:57
__BYTE_REG _IO[]
Definition: hardware.h:28
__REG OBP0_REG
Definition: hardware.h:297
__REG HDMA5_REG
Definition: hardware.h:343
__REG OCPS_REG
Definition: hardware.h:366
__REG WY_REG
Definition: hardware.h:301
__REG BCPD_REG
Definition: hardware.h:363
__REG SCY_REG
Definition: hardware.h:285
__REG NR32_REG
Definition: hardware.h:115
__BYTE_REG PCM_SAMPLE[16]
Definition: hardware.h:160
__REG BCPS_REG
Definition: hardware.h:359
__BYTES _RAMBANK[]
Definition: hardware.h:26
__BYTE_REG AUD3WAVE[16]
Definition: hardware.h:159
__REG WX_REG
Definition: hardware.h:303
__REG TMA_REG
Definition: hardware.h:63
__REG HDMA4_REG
Definition: hardware.h:341
#define __BYTE_REG
Definition: hardware.h:13
__REG NR13_REG
Definition: hardware.h:97
__REG PCM12_REG
Definition: hardware.h:376
__BYTE_REG _HRAM[]
Definition: hardware.h:30
__REG IF_REG
Definition: hardware.h:84
__REG NR43_REG
Definition: hardware.h:126
__REG NR41_REG
Definition: hardware.h:122
__REG HDMA3_REG
Definition: hardware.h:339
__REG LYC_REG
Definition: hardware.h:291
__REG VBK_REG
Definition: hardware.h:312
__REG SB_REG
Definition: hardware.h:55
__BYTE_REG rRAMG
Definition: hardware.h:34
__REG LCDC_REG
Definition: hardware.h:162
__REG TAC_REG
Definition: hardware.h:65
__REG NR24_REG
Definition: hardware.h:108
__BYTES _VRAM9000[]
Definition: hardware.h:21
__REG NR21_REG
Definition: hardware.h:102
__BYTES _OAMRAM[]
Definition: hardware.h:27
__BYTE_REG _AUD3WAVERAM[]
Definition: hardware.h:29
__REG KEY1_REG
Definition: hardware.h:305
__BYTES _VRAM8000[]
Definition: hardware.h:19
__REG RP_REG
Definition: hardware.h:351
__REG NR12_REG
Definition: hardware.h:95
__REG NR23_REG
Definition: hardware.h:106
__REG HDMA2_REG
Definition: hardware.h:337
__REG NR44_REG
Definition: hardware.h:130
__REG NR30_REG
Definition: hardware.h:111
__REG SCX_REG
Definition: hardware.h:287
__REG NR50_REG
Definition: hardware.h:133
__REG TIMA_REG
Definition: hardware.h:61
__REG OBP1_REG
Definition: hardware.h:299
__REG SVBK_REG
Definition: hardware.h:372
__REG IE_REG
Definition: hardware.h:382
__REG HDMA1_REG
Definition: hardware.h:335
#define __BYTES
Definition: hardware.h:12
__REG NR51_REG
Definition: hardware.h:141
__REG NR34_REG
Definition: hardware.h:119
__REG NR42_REG
Definition: hardware.h:124
__BYTES _RAM[]
Definition: hardware.h:25
__BYTE_REG rRAMB
Definition: hardware.h:37
__REG NR52_REG
Definition: hardware.h:153
__BYTES _SCRN0[]
Definition: hardware.h:22
__REG PCM34_REG
Definition: hardware.h:379
__REG STAT_REG
Definition: hardware.h:242
__REG NR11_REG
Definition: hardware.h:93
__REG NR10_REG
Definition: hardware.h:87
__BYTE_REG rROMB0
Definition: hardware.h:35
__REG DMA_REG
Definition: hardware.h:293
__REG OCPD_REG
Definition: hardware.h:370
__REG NR31_REG
Definition: hardware.h:113
__BYTES _VRAM[]
Definition: hardware.h:18
__REG LY_REG
Definition: hardware.h:289
__REG NR22_REG
Definition: hardware.h:104
__REG BGP_REG
Definition: hardware.h:295
__BYTES _VRAM8800[]
Definition: hardware.h:20
__REG DIV_REG
Definition: hardware.h:59
__BYTES _SCRN1[]
Definition: hardware.h:23